1. Field Of The Invention
The present invention relates to a serial transmission method in which a microprocessor directly controls the state of transmit and receive signals and in which a non-maskable interrupt pin of the microprocessor is used in connection with receipt of serial transmissions.
2. Incorporation By Reference
U.S. patent application Ser. No. 07/978,369, entitled "Method And Apparatus For Interfacing A Peripheral To A Local Area Network", is hereby incorporated by reference.
3. Description Of The Related Art
Serial communications are in nearly universal use as a simple technique for communicating between different computer processors. A suitable serial transmission convention is defined by IEEE RS-232 asynchronous serial transmission protocol, the contents of which are incorporated herein by reference. Such a protocol requires only two wires for serial transmission: a transmit wire and a receive wire. Data transmissions are received serially on the receive wire and transmitted serially on the transmit wire.
Data format for serial transmissions, whether received or transmitted, is simple: a data transmission is preceded by a start bit which is always a binary "1" and which alerts the receiver that data is being transmitted, followed by eight data bits which are mixed binary 1's and 0's in accordance with the data, and terminated by a stop bit (which is one, one-and-a-half, or two times as long as the start bit). A binary 1 is coded by a high voltage level, usually +3 to +15 volts, and a binary 0 is coded by a -3 to -15 volt level. Each of the bits is transmitted serially and is separated from adjacent bits by a time period inversely proportional to the transmit rate. Thus, for a typical 19,200 bits-per-second transmission rate, each bit is separated by 1/19.2 KHz, or 52 .mu.s.
A wide variety of devices have been proposed to convert the serial data bits transmitted on a serial interface into a conventional parallel format which is more easily used by today's processors. One such device is a universal asynchronous receiver transmitter (UART) which, in a receive mode, detects the start bit and then assembles the subsequent eight data bits into an 8-bit wide byte. The UART then interrupts the processor and provides the 8-bit byte to the processor.
Difficulties have been encountered in the arrangement described above in that before the UART can transmit its 8-bit byte to the processor, the processor must first respond to the UART's interrupt. There are many situations in which a processor would ignore such an interrupt. For example, the processor may be involved in computations which disable UART interrupts. As another example, the processor may be involved in erroneous computations caused, for example, by a hardware failure and therefore might never be able to respond to the UART's interrupt.
One typical use of a serial port is in connection with debugging capabilities provided for the processor. For example, the processor might provide debug information to a second processor so as to assist in determining erroneous or poorly understood operation of the processor. In those situations, having a serial port whose interrupt is ignored during erroneous operations of the processor, which is precisely the situation in which debug information is the most valuable, is a problem. Moreover, UART's add some cost and take up some space in the overall computer system. Consequently, UART's are usually provided on prototypes only, so that the final system does not incur a cost and space penalty. This is disadvantageous since it is therefore not possible to debug final systems for failures "in the field".